Logic Synthesis And Verification Algorithms
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| Google books | books.google.com |
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| Originally published | June 30, 1996 |
| Authors | Fabio Somenzi |
| Gary Deane Hachtel | |
| Editors | Fabio Somenzi |
| Date of Reg. | |
| Date of Upd. | |
| ID | 1953067 |
About Logic Synthesis And Verification Algorithms
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. . . .