SystemVerilog
| Use attributes for filter ! | |
| Filename extensions | sv,. svh |
|---|---|
| Typing discipline | weak |
| Designed by | Synopsys |
| Stable release | IEEE |
| February 22, 2018 | |
| Paradigm | Object-oriented |
| verification | |
| Date of Reg. | |
| Date of Upd. | |
| ID | 1274186 |
About SystemVerilog
SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. SystemVerilog is based on Verilog and some extensions, and since 2008 Verilog is now part of the same IEEE standard.
SystemVerilog Photos
